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M41T50
Serial Access Digital Input Real-Time Clock with Alarms
PRELIMINARY DATA
FEATURES SUMMARY

TIMEKEEPING DOWN TO 1.3V 1.7V TO 3.6V I2C BUS OPERATING VOLTAGE OPERATES FROM 50Hz OR 60Hz DIGITAL CLOCK SIGNAL COUNTERS FOR SECONDS, MINUTES, HOURS, DAY, DATE, MONTH, YEAR, AND CENTURY SERIAL INTERFACE SUPPORTS I2C BUS (400kHz) PROGRAMMABLE ALARM AND INTERRUPT FUNCTION 1Hz SQUARE WAVE OUTPUT LOW OPERATING CURRENT OF 350A AUTOMATIC LEAP YEAR COMPENSATION SOFTWARE PROGRAMMABLE OUTPUT (OUT) OPERATING TEMPERATURE OF -40 TO 85C LEAD-FREE 16-PIN QFN PACKAGE
Figure 1. Package
QFN16 (Q)
January 2005
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M41T50
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Table 1. Figure 3. Figure 4. Logic Diagram . . . . . . . . . . . . . . . . . . . . . Signal Names . . . . . . . . . . . . . . . . . . . . . 16-pin QFN Connections . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... .....4 .....4 .....4 .....5
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 5. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 6. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. Slave Address Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 9. Alternative READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 10.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Digital Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TIMEKEEPER(R) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 2. TIMEKEEPER(R) Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Setting Alarm Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 11.Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Century Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. Initial Power-on Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5. Century Bits Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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M41T50
Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 12.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 13.Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 10. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 14.QFN16 - 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Outline . . . . . . . . 19 Table 11. QFN16 - 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Mechanical Data . 20 Figure 15.QFN16 - 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Footprint . . . . . . . 20 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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M41T50
SUMMARY DESCRIPTION
The M41T50 Serial Access TIMEKEEPER(R) is a low power Serial RTC that does not require a crystal. The clock operates from a digital clock input pin at 50Hz or 60Hz. Eight registers (see Table 2., page 12) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 8 registers provide status/control of Alarm, Square Wave (1Hz), and 50Hz or 60Hz digital clock frequency selection functions. Addresses and data are transferred serially via a two line, bi-directional I2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte. Functions available to the user include a time-ofday clock/calendar, Alarm interrupts, and Square Wave output. The eight clock address locations contain the century, year, month, date, day, hour, minute, and seconds in 24-hour BCD format. Corrections for 28-, 29- (leap year), 30- and 31-day months are made automatically. The M41T50 is supplied in a 16-pin QFN.
Figure 2. Logic Diagram
VCC
Table 1. Signal Names
CLKIN SDA SCL Digital Clock Input (50Hz or 60Hz) Serial Data Input/Output Serial Clock Input Interrupt or OUT Output (Open Drain) Square Wave Output (Open Drain or Push-pull) Supply Voltage Ground
CLKIN SCL SDA M41T50
IRQ/OUT(1) SQW (1Hz)(2)
IRQ/OUT SQW (1Hz) VCC VSS
VSS
AI09110
Figure 3. 16-pin QFN Connections
CLKIN VCC 14 NC NC 13 12 11 10 9 5 VSS 6 NC 7 NC 8 NC NC IRQ/OUT(1) SCL SDA
Note: 1. Open Drain only. 2. Defaults to push-pull (SQW disabled) on power-up. May also be programmed to be Open Drain.
16 NC NC VSS SQW (1Hz)
(2)
15
1 2 3 4
AI09111
Note: 1. Open Drain only. 2. Defaults to push-pull (SQW disabled) on power-up. May also be programmed to be Open Drain.
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M41T50
Figure 4. Block Diagram
SQWE OUT AFE IRQ/OUT(2) SQW(1)
1 Hz CLKIN DIVIDER
ALARM SECONDS MINUTES HOURS
VCC VSS
CONTROL LOGIC
DAY DATE CENTURY/ MONTH
SCL
SERIAL BUS INTERFACE
SDA
ADDRESS REGISTER
YEAR
AI09112
Note: 1. May be configured as either push-pull or open drain. 2. Open drain only.
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M41T50
OPERATION
The M41T50 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 16 bytes contained in the device can then be accessed sequentially in the following order: 1. Reserved0 Register 2. Seconds Register 3. Minutes Register 4. Hours Register 5. Day Register 6. Date Register 7. Century/Month Register 8. Year Register 9. Out Register 10. Reserved1 Register 11 - 15. Alarm Registers 16. Flags Register 2-Wire Bus Characteristics The bus is intended for communication between different ICs. It consists of two lines: a bi-directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: - Data transfer may be initiated only when the bus is not busy. - During data transfer, the data line must remain stable whenever the clock line is High. - Changes in the data line, while the clock line is High, will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy. Both data and clock lines remain High. Start data transfer. A change in the state of the data line, from high to Low, while the clock is High, defines the START condition. Stop data transfer. A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition. Data Valid. The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called "transmitter," the receiving device that gets the message is called "receiver." The device that controls the message is called "master." The devices that are controlled by the master are called "slaves." Acknowledge. Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low during the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line High to enable the master to generate the STOP condition.
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M41T50
Figure 5. Serial Bus Data Transfer Sequence
DATA LINE STABLE DATA VALID
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
Figure 6. Acknowledgement Sequence
START SCL FROM MASTER 1 2 8 CLOCK PULSE FOR ACKNOWLEDGEMENT 9
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
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M41T50
READ Mode In this mode the master reads the M41T50 slave after setting the slave address (see Figure 8., page 9). Following the WRITE Mode Control Bit (R/W=0) and the Acknowledge Bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ Mode Control Bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an Acknowledge Bit to the slave transmitter. The address pointer is only incremented on reception of an Acknowledge Clock. The M41T50 slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to "An+2." Figure 7. Slave Address Location
R/W
This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume due to a Stop Condition or when the pointer increments to any non-clock address (08h-0Fh). Note: This is true both in READ Mode and WRITE Mode. An alternate READ Mode may also be implemented whereby the master reads the M41T50 slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 9., page 9).
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
AI00602
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M41T50
Figure 8. READ Mode Sequence
START START R/W BUS ACTIVITY: MASTER R/W
SDA LINE
S
WORD ADDRESS (An) ACK
S
DATA n
DATA n+1
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS STOP
DATA n+X
P
AI00899
Figure 9. Alternative READ Mode Sequence
START R/W STOP DATA n ACK ACK DATA n+1 ACK ACK DATA n+X P NO ACK
AI00895
BUS ACTIVITY: MASTER SDA LINE
S
BUS ACTIVITY: SLAVE ADDRESS
WRITE Mode In this mode the master transmitter transmits to the M41T50 slave receiver. Bus protocol is shown in Figure 10., page 10. Following the START condition and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed device that word address "An" will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next
NO ACK
and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. The M41T50 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address see Figure 7., page 8 and again after it has received the word address and each data byte.
ACK
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M41T50
Figure 10. WRITE Mode Sequence
START BUS ACTIVITY: MASTER R/W STOP WORD ADDRESS (An) ACK ACK DATA n DATA n+1 DATA n+X P ACK ACK
AI00591
SDA LINE
S
BUS ACTIVITY: SLAVE ADDRESS
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ACK
M41T50
CLOCK OPERATION
The eight byte clock register (see Table 2., page 12) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Reserved0, Seconds, Minutes, and Hours are contained within the first four registers. Bits D0 through D2 of Register 04h contain the Day (day of week). Registers 05h, 06h, and 07h contain the Date (day of month), Month, and Years. Bit D7 of Register 01h contains the STOP Bit (ST). Setting this bit to a '1' will cause the oscillator to stop. When reset to a '0' the oscillator restarts within one second (typical). Bits D6 and D7 of Clock Register 06h (Century/ Month Register) contain the CENTURY Bit 0 (CB0) and CENTURY Bit 1 (CB1). Bit D6 of Register 0Ch (Alarm Hour Register) contains the SQW Open Drain Bit (SQWOD). When this bit is set to '1,' the Square Wave output will become an open drain output and require a pull-up resistor. Note: A WRITE to ANY location within the first eight bytes of the clock register (00h-07h), including the 60Hz Bit and CB0-CB1 Bits will result in an update of the system clock and a reset of the divider chain. This could result in an inadvertent change of the current time. These non-clock related bits should be written prior to setting the clock, and remain unchanged until such time as a new clock time is also written. The eight Clock Registers may be read one byte at a time, or in a sequential block. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ. Digital Clock Input The M41T50 requires an external square wave clock source of 50Hz or 60Hz (45% to 55% duty cycle) for the clock function. Bit D7 (60Hz bit) of Register 05h (Date Register) is used to select between a 50Hz (60Hz Bit = '0') or a 60Hz (60Hz Bit = '1') clock input frequency signal. The 60Hz Bit defaults to '1' on power-up. TIMEKEEPER (R) Registers The M41T50 offers 16 internal registers which contain Clock, Alarm, and Flag Registers. The Clock registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORTTM TIMEKEEPER cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address (00h to 07h). The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer increments to a non-clock address. TIMEKEEPER and Alarm Registers store data in BCD format.
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M41T50
Table 2. TIMEKEEPER(R) Register Map
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh OUT 0 AFE RPT4 RPT3 RPT2 RPT1 0 0 ST 0 0 0 60Hz CB1 0 0 0 CB0 10 Years 0 0 SQWE RPT5 SQWOD 0 0 0 0 0 Al 10M 0 D6 0 D5 0 10 Seconds 10 Minutes 10 Hours 0 10 Date 10M 0 0 D4 0 D3 0 D2 0 Seconds Minutes Hours (24 Hour Format) Day of Week Date: Day of Month Month Year D1 0 D0 0 Function/Range BCD Format Reserved0 Seconds Minutes Hours Day Date Century/ Month Year 00-59 00-59 00-23 01-7 01-31 0-3/01-12 00-99
0
0
0
0
0
0
0
0
Out Reserved1 Al Month Al Date Al Hour Al Min Al Sec 01-12 01-31 00-23 00-59 00-59
Alarm Month Alarm Date Alarm Hour Alarm Minutes Alarm Seconds
AI 10 Date AI 10 Hour
Alarm 10 Minutes Alarm 10 Seconds AF 0 0 0
0
0
0
Flags
Keys: 0 = Must be set to '0' AF = Alarm Flag (Read only) AFE = Alarm Flag Enable Flag CB0-CB1 = Century Bits OUT = Output level
SQWOD = Square Wave output Open Drain Bit RPT1-RPT5 = Alarm Repeat Mode Bits SQWE = Square Wave Enable Bit ST = Stop Bit 60Hz = 50Hz or 60Hz Select Bit
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M41T50
Setting Alarm Clock Registers Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 3., page 13 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set, the alarm condition activates the IRQ/OUT pin. To disable the alarm, write '0' to the Alarm Date Register and to RPT5-RPT1. Figure 11. Alarm Interrupt Reset Waveform
0Eh 0Fh 00h
Note: If the address pointer is allowed to increment to the Flag Register address, an alarm condition will not cause the Interrupt/Flag to occur until the address pointer is moved to a different address. It should also be noted that if the last address written is the "Alarm Seconds," the address pointer will increment to the Flag address, causing this situation to occur. The IRQ output is cleared by a READ to the Flags Register as shown in Figure 11., page 13. A subsequent READ of the Flags Register is necessary to see that the value of the Alarm Flag has been reset to '0.'
ALARM FLAG BIT (AF)
IRQ/OUT
HIGH-Z
AI09113
Table 3. Alarm Repeat Modes
RPT5 1 1 1 1 1 0 RPT4 1 1 1 1 0 0 RPT3 1 1 1 0 0 0 RPT2 1 1 0 0 0 0 RPT1 1 0 0 0 0 0 Alarm Setting Once per Second Once per Minute Once per Hour Once per Day Once per Month Once per Year
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M41T50
Square Wave Output The M41T50 offers the user a 1Hz square wave function which is output on the SQW pin. The SQW pin can be turned on and off under software control with the Square Wave Enable Bit (SQWE) located in Register 0Ah. The SQW output is programmable as an N-channel, open drain output driver, or a full CMOS output driver. The initial power-up default for the SQW output is disabled, in the full-CMOS (or Push-pull mode). By setting the Square Wave Open Drain Bit (SQWOD in address 0Ch) to a '1,' the output will be configured as an open drain (with IOL as specified in Table 9., page 17). When SQWOD is set to '0,' the output will be configured as fullCMOS (sink and source current as specified in Table 9., page 17). Note: When configured as Open Drain (SQWOD = '1'), the SQW pin requires an external pull-up resistor. Table 4. Initial Power-on Default Values
Condition Initial Power-up(1) ST 0 SQWOD 0 OUT 1 AFE 0 SQWE 0 60Hz 1
Century Bits These two bits will increment in a binary fashion at the turn of the century, and handle all leap years correctly. See Table 5., page 14 for additional explanation. Output Driver Pin When the AFE Bit is not set to generate an interrupt, the IRQ/OUT pin becomes an output driver that reflects the contents of D7 of the Out Register. In other words, when D7 (OUT Bit) is a '0,' then the IRQ/OUT pin will be driven low. Note: The IRQ/OUT pin is an open drain which requires an external pull-up resistor. Initial Power-on Defaults Upon application of power to the device, the register bits will initially power-on in the state indicated in Table 4.
Note: 1. All other control bits power-up in an undetermined state.
Table 5. Century Bits Examples
CB0 0 0 1 1 CB1 0 1 0 1 Leap Year? Yes No No No Example(1) 2000 2100 2200 2300
Note: 1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by 100. The only exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year 2100 is not).
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M41T50
MAXIMUM RATING
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 6. Absolute Maximum Ratings
Sym TSTG VCC TSLD(1) VIO IO PD Parameter Storage Temperature (VCC Off) Supply Voltage Lead Solder Temperature for 10 Seconds Input or Output Voltages Output Current Power Dissipation Value -55 to 125 -0.3 to 4.6 260 -0.2 to Vcc+0.2 20 1 Unit C V C V mA W
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
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M41T50
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 7. Operating and AC Measurement Conditions
Parameter Supply Voltage (VCC) Ambient Operating Temperature (TA) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
Note: 1. 0.2VCC to 0.9VCC for CLKIN input (pin 16)
M41T50 1.7V to 3.6V -40 to 85C 50pF 5ns 0.2VCC to 0.8 VCC(1) 0.3VCC to 0.7 VCC
Figure 12. AC Measurement I/O Waveform
0.8VCC
0.7VCC 0.3VCC
AI02568
0.2VCC
Table 8. Capacitance
Symbol CIN COUT(3) tLP Input Capacitance Output Capacitance Low-pass filter input time constant (SDA and SCL) Parameter(1,2) Min Max 7 10 50 Unit pF pF ns
Note: 1. Effective capacitance measured with power supply at 3.6V; sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
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M41T50
Table 9. DC Characteristics
Symb ol VCC Parameter Test Condition(1) Clock Operating Voltage I2C bus (400kHz) VCC = 3.6V ICC1 Supply Current SCL = 400kHz (No load) VCC = 3.0V VCC = 2.5V VCC = 2.0V 3.6V SCL = 0Hz All inputs(2) VCC - 0.2V VSS + 0.2V SQW On (Open Drain) 3.0V 2.0V 3.6V SQW Off 3.0V 2.0V VIL VIH VOL VOH Input Low Voltage Input High Voltage VCC = 3.6V, IOL = 3.0mA (SDA) Output Low Voltage VCC = 3.6V, IOL = 1.0mA (IRQ/OUT, SQW) Output High Voltage Pull-up Supply Voltage (Open Drain) ILI ILO Input Leakage Current Output Leakage Current VCC = 3.6V, IOH = -1.0mA (Push-Pull only) IRQ/OUT, SQW (1Hz) 0V VIN VCC(2) 0V VOUT VCC 2.4 3.6 1 1 0.4 V V V A A -0.2 0.9VCC 0.65 0.6 0.3VCC VCC+0.2 0.4 1.2 0.9 0.7 350 300 250 1.3 Min 1.3 1.7 Typ Max 3.6 3.6 400 Unit V V A A A A A A A A A A V V V
ICC2
Supply Current (standby)
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 1.7V to 3.6V (except where noted). 2. CLKIN pin = VSS or VCC.
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M41T50
Figure 13. Bus Timing Requirements Sequence
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tSU:STO tF tHD:STA
AI00589
Table 10. AC Characteristics
Sym fSCL tLOW tHIGH tR tF tHD:STA tSU:STA tSU:DAT(2) tHD:DAT tSU:STO tBUF Parameter(1) SCL Clock Frequency Clock Low Period Clock High Period SDA and SCL Rise Time SDA and SCL Fall Time START Condition Hold Time (after this period the first clock pulse is generated) START Condition Setup Time (only relevant for a repeated start condition) Data Setup Time Data Hold Time STOP Condition Setup Time Time the bus must be free before a new transmission can start 600 600 100 0 600 1.3 Min 0 1.3 600 300 300 Typ Max 400 Units kHz s ns ns ns ns ns ns s ns s
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 1.7V to 3.6V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
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M41T50
PACKAGE MECHANICAL INFORMATION
Figure 14. QFN16 - 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Outline
D
E
A3
A1
A
ddd C
b L
e K
1 2
E2
3
Ch
K D2
QFN16-A
Note: Drawing is not to scale.
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M41T50
Table 11. QFN16 - 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Mechanical Data
mm Symb Typ A A1 A3 b D D2 E E2 e K L ddd Ch N 0.90 0.02 0.20 0.25 3.00 1.70 3.00 1.70 0.50 0.20 0.40 - - Min 0.80 0.00 - 0.18 2.90 1.55 2.90 1.55 - - 0.30 0.08 0.33 16 Max 1.00 0.05 - 0.30 3.10 1.80 3.10 1.80 - - 0.50 - - Typ 0.035 0.001 0.008 0.010 0.118 0.067 0.118 0.067 0.020 0.008 0.016 - - Min 0.032 0.000 - 0.007 0.114 0.061 0.114 0.061 - - 0.012 0.003 0.013 16 Max 0.039 0.002 - 0.012 0.122 0.071 0.122 0.071 - - 0.020 - - inches
Figure 15. QFN16 - 16-lead, Quad, Flat Package, No Lead, 3x3mm, Recommended Footprint
1.60
3.55
2.0
AI09126
Note: Substrate pad should be tied to VSS.
0.28
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M41T50
PART NUMBERING
Table 12. Ordering Information Scheme
Example: M41T 50 Q 6 F
Device Family M41T
Device Type and Supply Voltage 50 = VCC = 1.7V to 3.6V
Package Q = QFN16
Temperature Range 6 = -40C to 85C
Shipping Method for SOIC F = Lead-free Package (ECO PACK(R)), Tape & Reel
For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you.
21/23
M41T50
REVISION HISTORY
Table 13. Document Revision History
Date December 12, 2003 25-Dec-03 15-Jan-04 27-Feb-04 02-Mar-04 26-Apr-04 13-May-04 18-Jan-05 Version 1.0 1.1 1.2 1.3 1.4 2.0 3.0 4.0 First Edition Add crystal isolation, footprint (Figure 13) Update characteristics (Figure 2, 3, 13; Table 2, 4, 9, 11, 12) Update characteristics, mechanical information (Figure 4, 14, 15; Table 6, 9, 11) Update characteristics (Table 7, 9, 10, 12) Reformat and publish Update characteristics (Table 6, 9, 10; Figure 2, 3, 15) Update characteristics (Figure 4; Table 2, 7, 9) Revision Details
M41T50, 41T50, T50, T62, T63, T64, T65, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, vIndustrial, Industrial, Industrial, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC
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M41T50
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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